1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a reading method of a non-volatile memory device.
2. Description of the Related Art
A nonvolatile memory device retains stored data even when power is interrupted. Each memory cell of a non-volatile memory device includes a floating gate that is controlled by a control gate. Also, each memory cell writes or erases data by accumulating or discharging electrons to or from the floating gate.
FIG. 1 is a circuit diagram of a conventional non-volatile memory device. In particular, each memory cell includes one floating gate and two control gates disposed adjacent to the floating gate.
Referring to FIG. 1, the conventional non-volatile memory device includes a plurality of strings, a plurality of bit lines BL, and a plurality of source lines SL. Each bit lines BL is coupled with a first end of each string, and the source line SL is coupled in common with a second end of each string. Each string includes a drain selection transistor DST, a plurality of memory cells MC0 to MC3, and a source selection transistor SST.
A gate of the drain selection transistor DST extends in a first direction to form a drain selection line DSL, and a gate of the source selection transistor SST extends in the first direction to form a source selection line SSL.
Each of the memory cells MC0 to MC3 includes one floating gate FG and two control gates CG disposed adjacent to the floating gate FG. For example, the memory cell MC0 includes the floating gate FG0 and the control gates CG0 and CG1 disposed on both sides of the floating gate FG0. The control gates extend in the first direction to form word lines WL.
The conventional non-volatile memory device may increase the coupling ratio of a floating gate and control gates.
However, since the conventional non-volatile memory device has a structure where adjacent memory cells share one control gate, when a program voltage or a read voltage is applied to the two control gates included in a selected memory cell to perform a program operation or a read operation, the memory cells adjacent to the selected memory cell are affected. For example, when a program operation is performed and a program voltage is applied to the two control gates of a selected memory cell, the program voltage is applied to a control gate of the selected memory cell and the control gates of unselected memory cells adjacent to the selected memory cell. Therefore, adjacent memory cells may be programmed, which may be referred to as a program disturbance. However, the features that may be caused during a read operation are not known.